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? semiconductor components industries, llc, 2005 march, 2005 ? rev. 3 1 publication order number: ncp4896/d ncp4896 1.0 watt audio power amplifier with earpiece driving capability the ncp4896 is an audio power amplifier designed for portable communication device applications such as mobile phones. this part is capable of delivering 1.0 w of continuous average power to an 8.0 btl load from a 5.0 v power supply and, 250 mw to a 4.0 btl from 2.6 v power supply. it also provides the control of driving a single?ended earpiece and delivers 90 mw from a 5.0 v power supply to a 32 load. this device provides high quality audio while requiring few external components and minimal power consumption. it features a low?power consumption shutdown mode, which is achieved by driving the shutdown pin with logic low. the ncp4896 contains circuitry to prevent from apop and clicko noise that would otherwise occur during turn?on and turn?off transitions. it is also efficient when switching modes from btl to se and se to btl. for maximum flexibility, the part provides an externally controlled gain (with resistors), as well as an externally controlled turn?on time (with bypass capacitor). due to its excellent psrr, it can be directly connected to the battery, saving the use of an ldo. features ? single?ended or differential control ? 1.0 w to an 8.0 btl load from a 5.0 v power supply ? excellent psrr: direct connection to the battery ? ultra low current shutdown mode ? 2.2 v?5.5 v operation ? external gain configuration capability ? external turn?on time configuration capability ? thermal overload protection circuitry ? up to 1.0 nf capacitive load driving capability ? apop and clicko noise protection circuit ? this is a pb?free device typical applications ? portable electronic devices ? pdas ? mobile phones 9?pin flip?chip fc suffix case 499al pin connections 9?pin flip?chip csp xxx = specific device code a = assembly location y = year ww = work week marking diagram a3 b3 c3 a2 b2 c2 a1 b1 c1 se/btl byp outb vp nc vm inm sd outa (top view) 1 see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information xxx ayww a1 a3 c1 http://onsemi.com
ncp4896 http://onsemi.com 2 figure 1. typical ncp4896 application circuit with single?ended input ? + vp inm vp vp 8.0 loud speaker outa outb r1 20 k vmc bridge bypass 20 k 1 f 390 nf shutdown control 20 k 1 f cs rin cin audio input ? + 20 k r2 vm bypass bypass c b vih se/btl shutdown vil se d c o 47 f mono jack 16 or 32 earpiece rf pin description pin type symbol description a1 i se/btl when this pin is low , the audio amplifier is in dif ferential mode. if a high level is applied, the configuration is in single?ended mode a2 i byp bypass capacitor pin which provides the common mode voltage (vp/2). a3 o outb positive output of the amplifier. in high impedance state when the device is in single?ended mode. b1 i vp positive analog supply of the cell. b2 nc not connected. b3 i vm ground. c1 i inm audio input signal. c2 i sd the device enters in shutdown mode when a low level is applied to this pin. c3 o outa negative output of the amplifier. this is the active output dedicated to a se load when this configuration is activated.
ncp4896 http://onsemi.com 3 maximum ratings (note 1) rating symbol value unit supply voltage vp 6.0 v operating supply voltage op vp 2.2 to 5.5 v ? input v oltage v in ?0.3 to vcc +0.3 v max output current iout 500 ma power dissipation (note 2) pd internally limited ? operating ambient t emperature t a ?40 to +85 c max junction temperature t j 150 c storage temperature range t stg ?65 to +150 c thermal resistance junction?to?air r ja 90 c/w ja (note 3) esd protection human body model (hbm) (note 4) machine model (mm) (note 5) ? > 2000 > 200 v latch up current at t a = 85 c (note 6) ? 100 ma ? maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limi t values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = +25 c. 2. the thermal shutdown set to 160 c (typical) avoids irreversible damage on the device due to power dissipation. 3. for the 9?pin flip?chip csp package, the r ja is highly dependent of the pcb heatsink area. for example, r ja can equal 195 c/w with 50 mm 2 total area and also 135 c/w with a 500 mm 2 area. 4. human body model, 100 pf discharge through a 1.5 k resistor following specification jesd22/a114. 5. machine model, 200 pf discharged through all pins following specification jesd22/a115. 6. maximum ratings per jedec standard jesd78.
ncp4896 http://onsemi.com 4 electrical characteristics limits apply for t a between ?40 c to +85 c (unless otherwise noted). characteristic symbol conditions min (note 7) typ max (note 7) unit supply quiescent current i dd vp = 3.0 v, no load vp = 5.0 v, no load btl ? ? 1.7 1.8 ? ma vp = 3.0 v, 8.0 btl vp = 5.0 v, 8.0 btl ? ? 1.8 2.0 ? 4.0 vp = 5.0 v, no load, se ? 1.0 2.5 vp = 5.0 v, 32 se ? 1.1 ? ma common mode v oltage v cm ? vp/2 ? v shutdown current i sd for vp between 2.2 v to 5.5 v sd = low t a = +25 c t a = ?40 c to +85 c ? ? ? ? 20 ? ? 600 2.0 na a shutdown voltage high v sdih ? 1.4 ? ? v shutdown voltage low v sdil ? ? ? 0.4 v se select v btl/se ? 1.4 ? ? v de select v se/btl ? ? ? 0.4 v turning on time (note 8) t wu c by = 1.0 f ? 140 ? ms turning off time (note 8) t sd ? ? 20 ? ms output swing v loadpeak vp = 3.0 v, 8.0 , btl vp = 5.0 v, 8.0 btl 2.3 ? 2.57 4.3 ? ? v vp = 5.0 v, 32 se ? 4.9 ? v rms output power p o vp = 5.0 v, 32 se thd + n < 0.1% vp = 5.0 v, 16 , se thd + n < 0.1% vp = 5.0 v, 8.0 , btl thd + n < 0.1% ? ? ? 92 176 1080 ? ? ? mw output offset voltage v os for vp between 2.2 v to 5.5 v btl and se ?30 1.0 30 mv power supply rejection ratio psrr v+ rf = ri 20 k vp ripple_pp = 200 mv c by = 1.0 f input terminated with 10 f = 217 hz to 1.0 khz vp = 5.0 v, 8.0 btl vp = 3.0 v, 8.0 btl vp = 5.0 v, 32 se vp = 3.0 v, 32 se ? ? ? ? ?66 ?67 ?69 ?70 ? ? ? ? db efficiency vp = 3.0 v, 8.0 btl p orms = 380 mw vp = 5.0 v, 8.0 btl p orms = 1.0 w ? ? 64 63 ? ? % thermal shutdown t emperature t sd ? ? 160 ? c total harmonic distortion thd + n rf = ri 20 k vp = 3.6 v, f = 1.0 khz p out = 400 mw, 8.0 , btl p out = 40 mw, 16 , btl p out = 40 mw, 32 se ? ? ? 0.02 0.01 0.003 ? ? ? % 7. min/max limits are guaranteed by design, test or statistical analysis. 8. see section aapplication informationo for a theoretical approach of this parameter.
ncp4896 http://onsemi.com 5 typical performance characteristics figure 2. thd + n vs. power out (btl mode) 0 200 400 1000 10 0.001 0.1 thd + n (%) p out , power out (mw) vp = 5.0 v rf = ri 20 k btl mode r l = 8 f = 1.0 khz 1 600 800 1200 0.01 figure 3. thd + n vs. power out (btl mode) 0 100 200 300 10 0.001 0.1 thd + n (%) p out , power out (mw) figure 4. thd + n vs. power out (btl mode) 0 100 200 300 500 10 0.01 0.1 thd + n (%) p out , power out (mw) 1 400 500 1 0.01 400 figure 5. thd + n vs. frequency (btl mode) 10 100 1000 10,000 100,00 0 1 0.001 0.1 thd + n (%) frequency (hz) 0.01 figure 6. thd + n vs. frequency (btl mode) 10 100 1000 10,000 100,000 1 0.001 0.1 thd + n (%) frequency (hz) 0.01 figure 7. thd + n vs. frequency (btl mode) 10 100 1000 10,000 100,00 0 0.001 0.1 thd + n (%) frequency (hz) 0.01 vp = 3.0 v rf = ri 20 k btl mode r l = 8 f = 1.0 khz vp = 2.6 v rf = ri 20 k btl mode r l = 4 f = 1.0 khz vp = 5.0 v rf = ri 20 k btl mode r l = 8 p out = 250 mw vp = 3.0 v rf = ri 20 k btl mode r l = 8 p out = 250 mw vp = 2.6 v rf = ri 20 k btl mode r l = 8 p out = 100 mw
ncp4896 http://onsemi.com 6 typical performance characteristics 0.001 0.010 0.100 1.000 10.000 020406080 100 figure 8. thd + n vs. output power (se mode) thd + n (%) output power (mw) vp = 5.0 v rf = ri 20 k se mode r l = 32 f = 1.0 khz 0.001 0.010 0.100 1.000 10.000 0 10203040 figure 9. thd + n vs. output power (se mode) thd + n (%) output power (mw) vp = 3.0 v rf = ri 20 k se mode r l = 32 f = 1.0 khz 0.001 0.010 0.100 1.000 10.000 0202530 15 figure 10. thd + n vs. output power (se mode) thd + n (%) output power (mw) vp = 2.6 v rf = ri 20 k se mode r l = 32 f = 1.0 khz 10 5.0 10 100 1000 10000 10000 0 0.001 0.010 0.100 1.000 figure 11. thd + n vs. frequency (se mode) thd + n (%) frequency (hz) vp = 4.2 v rf = ri 20 k se mode r l = 32 p out = 50 mw figure 12. psrr (btl mode) @ vp = 2.6 v 10 100 1000 10000 100000 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 13. psrr (btl mode) @ vp = 3.6 v 10 100 1000 10000 10000 0 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vp = 3.6 v rf = ri 20 k , c b = 1.0 f btl mode r l = 8 v ripple = 200 mv pk?pk vp = 2.6 v rf = ri 20 k , c b = 1.0 f btl mode r l = 8 v ripple = 200 mv pk?pk
ncp4896 http://onsemi.com 7 typical performance characteristics 10 100 1000 10000 100000 psrr (db) frequency (hz) vp = 3.6 v rf = ri 20 k btl mode r l = 8 v ripple = 200 mv pk?pk ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 14. psrr (btl mode) @ vp = 5.0 v 10 100 1000 10000 100000 psrr (db) frequency (hz) vp = 5.0 v rf = ri 20 k , c b = 1.0 f btl mode r l = 8 v ripple = 200 mv pk?pk ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 15. psrr vs. c b (btl mode) @ vp = 3.6 v c b =0.47 f c b =1.0 f c b = 4.7 f 10 100 1000 10000 100000 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 16. psrr vs. gain (btl mode) @ vp = 3.6 v gain = 1 gain = 5 10 100 1000 10000 10000 0 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 17. psrr (se mode) @ vp = 2.6 v 10 100 1000 10000 100000 psrr (db) frequency (hz) vp = 3.6 v rf = ri 20 k , c b = 1.0 f se mode r l = 32 v ripple = 200 mv pk?pk ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 18. psrr (se mode) @ vp = 3.6 v vp = 2.6 v rf = ri 20 k , c b = 1.0 f se mode r l = 32 v ripple = 200 mv pk?pk 10 100 1000 10000 10000 0 psrr (db)r frequency (hz) vp = 5.0 v rf = ri 20 k , c b = 1.0 f se mode r l = 32 v ripple = 200 mv pk?pk ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 19. psrr (se mode) @ vp = 5.0 v vp = 3.6 v rf = ri 20 k and rf = ri 100 k btl mode r l = 8 v ripple = 200 mv pk?pk
ncp4896 http://onsemi.com 8 typical performance characteristics 10 100 1000 10000 100000 psrr (db) frequency (hz) vp = 3.6 v rf = ri 20 k se mode r l = 32 v ripple = 200 mv pk?pk ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 20. psrr vs. c b (se mode) @ vp = 3.6 v c b =0.47 f c b =1.0 f c b = 4.7 f 10 100 1000 10000 100000 psrr (db) frequency (hz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 21. psrr vs. gain (se mode) @ vp = 3.6 v gain = 1 gain = 5 figure 22. output noise voltage (btl mode) @ vp = 3.6 v vp = 3.6 v rf = ri 20 k and rf = ri 100 k se mode r l = 8 v ripple = 200 mv pk?pk 10 100 1000 10000 output noise voltage ( vrms) frequency (hz) vp = 3.6 v rf = ri 20 k btl mode r l = 8 0 10 20 30 40 50 ncp4896 off ncp4896 on figure 23. output noise voltage (se mode) @ vp = 3.6 v 10 100 1000 10000 output noise voltage ( vrms) frequency (hz) vp = 3.6 v rf = ri 20 k se mode r l = 32 0 10 20 30 40 50 ncp4896 off ncp4896 on i dd , (ma) temperature (c ) rf = ri = 20 btl mode r l = 8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ?40 ?15 10 35 60 85 figure 24. quiescent current (btl mode) vs. vp vp = 3.0 v vp = 2.2 v vp = 5.5 v vp = 5.0 v i dd , (ma) temperature (c ) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ?40 ?15 10 35 60 85 figure 25. quiescent current (se mode) vs. vp 2.0 1.9 1.8 1.7 vp = 3.0 v vp = 2.2 v vp = 5.5 v vp = 5.0 v rf = ri = 20 se mode r l =32
ncp4896 http://onsemi.com 9 typical performance characteristics vp = 3.6 v rf = ri 20 k , c b = 1.0 f btl mode r l = 8 figure 26. turn on sequence (btl mode) @ vp = 3.6 v
ncp4896 http://onsemi.com 10 typical performance characteristics figure 27. power dissipation vs. output power 0 0.2 0.7 0 0.1 p d , power dissipation (w) p out , output power (w) figure 28. power dissipation vs. output power 0 0.1 0.2 0.3 0.3 0 0.1 p d , power dissipation (w) p out , output power (w) vp = 5 v r l = 8 f = 1 khz thd + n < 0.1% vp = 3.3 v r l = 8 f = 1 khz thd + n < 0.1% 0.5 0.4 0.6 0.8 1 1.2 0.2 0.4 0.5 0.2 0.3 0.4 0.6 0.05 0.15 0.25 figure 29. power dissipation vs. output power 0 0.1 0.2 0.3 0.4 0.25 0 0.05 p d , power dissipation (w) p out , output power (w) figure 30. power dissipation vs. output power 0 0.05 0.1 0.15 0.4 0.4 0 0.1 p d , power dissipation (w) p out , output power (w) vp = 3 v r l = 8 f = 1 khz thd + n < 0.1% 0.1 0.15 0.2 0.2 0.25 0.3 0.35 0.05 0.2 0.15 0.3 0.25 0.35 vp = 2.6 v f = 1 khz thd + n < 0.1% r l = 8 r l = 4 figure 31. power derating ? 9?pin flip?chip csp 0 20 160 700 0 p d , power dissipation (mw) t a , ambient temperature ( c) figure 32. maximum die temperature vs. pcb heatsink area 50 100 250 180 40 60 die temperature ( c) @ ambient temperature 25 c pcb heatsink area (mm 2 ) 120 150 200 100 200 300 400 500 600 80 100 160 140 p dmax = 633 mw for vp = 5 v, r l = 8 40 60 80 100 120 140 pcb heatsink area 500 mm 2 50 mm 2 200 mm 2 300 maximum die temperature 150 c vp = 2.6 v vp = 5 v vp = 3.3 v vp = 4.2 v
ncp4896 http://onsemi.com 11 application information detailed description the ncp4896 audio amplifier can operate from 2.2 v until 5.5 v power supply. it delivers 320 mw rms output power to 4.0 load (vp = 2.6 v) and 1.0 w rms output power to 8.0 load (vp = 5.0 v). the structure of the ncp4896 is basically composed of two identical internal power amplifiers. both are externally configurable with gain?setting resistors r in and rf (the closed?loop gain is fixed by the ratios of these resistors). so the load is driven differentially through outa and outb outputs. this configuration eliminates the need for an output coupling capacitor. internal power amplifier the output pmos and nmos transistors of the amplifier were designed to deliver the output power of the specifications without clipping. the channel resistance (r on ) of the nmos and pmos transistors does not exceed 0.6 when they drive current. the structure of the internal power amplifier is composed of three symmetrical gain stages, first and medium gain stages are transconductance gain stages to obtain maximum bandwidth and dc gain. turn?on and turn?off transitions a cycle with a turn?on and turn?off transition is illustrated with plots that show both single ended signals on the previous page. in order to eliminate apop and clicko noises during transitions, output power in the load must be slowly established or cut. when logic high is applied to the shutdown pin, the bypass voltage begins to rise exponentially and once the output dc level is around the common mode voltage, the gain is established slowly (20 ms). this way to turn?on the device is optimized in terms of rejection of apop and clicko noises. a theoretical value of turn?on time at 25 c is given by the following formula. c by : bypass capacitor r: internal 150 k resistor with a 25% accuracy t on = 0.95 * r * c by the device has the same behavior when it is turned?off by a logic low on the shutdown pin. during the shutdown mode, amplifier outputs are connected to the ground. however, to cut totally the output audio signal, you only need to wait for 20 ms. shutdown function the device enters shutdown mode when the shutdown signal is low. during the shutdown mode, the dc quiescent current of the circuit is typically 10 na. current limit circuit the maximum output power of the circuit (porms = 1.0 w, vp = 5.0 v, r l = 8.0 ) requires a peak current in the load of 500 ma. in order to limit the excessive power dissipation in the load when a short?circuit occurs, the current limit in the load is fixed to 800 ma. the current in the four output mos transistors are real?time controlled, and when one current exceeds 800 ma, the gate voltage of the mos transistor is clipped and no more current can be delivered. single?ended operation in se mode, the load is driven from the primary amplifier output (outa). the gain is set by the ration between rf and ri. se gain ? rf ri in this se mode, an output capacitor (co) is required to block the common mode voltage at the output of the amplifier, thus avoiding dc currents in the load. as for the high pass filter due to the input capacitor and the ri resistor, the load gives with co another first order high pass filter, the cut?off frequency of which is given by: fc 1 2
r l co se/btl operation due to the internal control of each amplifier through se/btl pin, the ncp4896 allows a cost saving for application which requires to drive a example an 8.0 btl and a single?ended load. the internal circuitry avoids apop and clicko noises that could occur in both btl and singled?ended loads during transitions from se to btl and btl to se.
ncp4896 http://onsemi.com 12 thermal overload protection internal amplifiers are switched off when the temperature exceeds 160 c, and will be switched on again only when the temperature decreases below 140 c. the ncp4896 is unity?gain stable and requires no external components besides gain?setting resistors, an input coupling capacitor and a proper bypassing capacitor in the typical application. both internal amplifiers are externally configurable (rf and r in ) with gain configuration. the differential?ended amplifier presents two major advantages: ? the possible output power is four times larger (the output swing is doubled) as compared to a single?ended amplifier under the same conditions. ? output pins (outa and outb) are biased at the same potential vp/2, this eliminates the need for an output coupling capacitor required with a single?ended amplifier configuration. the differential closed loop?gain of the amplifier is given by a vd * r f r in v orms v inrms . v orms is the rms value of the voltage seen by the load and v inrms is the rms value of the input differential signal. output power delivered to the load is given by p orms (vopeak) 2 2*r l (vopeak is the peak differential output voltage). when choosing gain configuration to obtain the desired output power, check that the amplifier is not current limited or clipped. the maximum current which can be delivered to the load is 500 ma i opeak v opeak r l . gain?setting resistor selection (r in and rf) r in and rf set the closed?loop gain of both amplifier. in order to optimize device and system performance, the ncp4896 should be used in low gain configurations. the low gain configuration minimizes thd + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations. a closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance. an input resistor (r in ) value of 22 k is realistic in most of applications, and doesn't require the use of a too large capacitor c in . input capacitor selection (c in ) the input coupling capacitor blocks the dc voltage at the amplifier input terminal. this capacitor creates a high?pass filter with rin, the cut?off frequency is given by fc 1 2* *r in *c in . the value of the capacitor must be high enough to ensure good coupling at low frequencies without attenuation. however a large input coupling capacitor requires more time to reach its quiescent dc voltage (vp/2) and can increase the turn?on pops. an input capacitor value between 0.1 and 0.39 f performs well in many applications (with r in = 22 k ). bypass capacitor selection (cby) the bypass capacitor cby provides half?supply filtering and determines how fast the ncp4896 turns on. this capacitor is a critical component to minimize the turn?on pop. a 1.0 f bypass capacitor value (c in = < 0.39 f) should produce clickless and popless shutdown transitions. the amplifier is still functional with a 0.1 f capacitor value but is more susceptible to apop and clicko noises. thus, a 1.0 f bypassing capacitor is recommended.
ncp4896 http://onsemi.com 13 figure 33. typical ncp4896 application circuit with single?ended input ? + vp inm vp vp outa outb 20 k vmc bridge bypass 20 k 1 f 1 f bias control 20 k 1 f cs r2 c2 audio input ? + 20 k vm bypass bypass c4 se/btl shutdown 47 f 16 or 32 earpiece in u2 or j5 r1 rl 8 j6 vp j13 j12 r4 100 k j18 j1 vp gnd tp3 j5 j9 j8 j19 j20 r7 j10 j11 vp c5 100 nf 100 k r6 100 k shutdown input se/btl input 1 k c o r5 tp4 tp5 vp u1 audio input u2
ncp4896 http://onsemi.com 14 bottom layer top layer figure 34. demonstration board for 9?pin flip?chip csp device ? pcb layers silkscreen layer
ncp4896 http://onsemi.com 15 bill of material item part description ref pcb footprint manufacturer manufacturer reference 1 ncp4896 audio amplifier u1 ncp4896 2 3.5 mm pcb jack connector u2 decelect?forgos (eurosab) iem101?3 3 smd resistor 20 k r1, r2 0805 vishnay?draloric crcw0805 4 smd resistor 100 k r4, r6, r7 0805 vishnay?draloric crcw0805 5 smd resistor 1.0 k r5 0805 vishnay?draloric crcw0805 6 ceramic capacitor 1.0 f, 16 v, x7r c1, c2, c4 0805 murata grm21 series grm21br71c105ka01l 7 tantalum capacitor 47 f, 6.3 v c3 b size avx tps series 8 ceramic capcitor 100 nf, 50 v, x7r c5 0805 murata grm21 series grm21br71h104ka01l 9 jumper header vertical mount, 2*1, 100 mils j10, j11, j12, j13, j19, j20 10 jumper connector, 400 mils j18 11 i/o connector. it can be plugged by blz5.08/2 (weidmuller reference) j1, j5, j6 weidmuller sl5.08/2/90b 12 smb connector j4, j8, j9 radiall r114665000 13 test point tp3, tp4, tp5 keystone 5000 ordering information device marking package shipping 2 NCP4896FCT1G mam 9?pin flip?chip (pb?free) 3000/t ape and reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp4896 http://onsemi.com 16 package dimensions 9?pin flip?chip fc suffix case 499al?01 issue o mm inches scale 20:1 0.265 0.01 0.50 0.0197 0.50 0.0197 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e d ?a? ?b? 0.10 c a2 a a1 ?c? 0.05 c 0.10 c 4 x seating plane d1 e e1 e 0.05 c 0.03 c a b 9 x b c b a 12 3 side view top view bottom view dim min max millimeters a 0.540 0.660 a1 0.210 0.270 a2 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. d 1.450 bsc e 0.330 0.390 b 0.290 0.340 e 0.500 bsc d1 1.000 bsc e1 1.000 bsc 1.450 bsc on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp4896/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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